Forward error correction (FEC), usually implemented by Reed-Solomon generation of parity symbols, is a desirable features of Ethernet point-to-point links. However, existing protocols for Ethernet point-to-point links, at least those operating at 1 Gb/s, either do not provide FEC or do so in a manner which imposes a degradation of the data rate or a substantial variable latency in the link.
For example, in the ITU-T recommendation G.709 “Interfaces for Optical Transport Network (OTN)” an FEC scheme that operates on OTN frames is defined, where each frame is a fixed size and FEC imposes a data throughput degradation.
IEEE 802.3 Clause 65, which is addressed to a 1 Gigabit per second Ethernet Passive Optical Network (EPON), does include a FEC option but operates for a point to multipoint architecture that forces the Ethernet preamble to be overwritten with a logical link identifier (LLID), mode and start of LLID delimiter (SLD) fields. It forces the media access control (MAC) to implement interpacket gap (IPG) stretching to accommodate the FEC parity symbols and therefore degrades the data throughput by at least 7%. Moreover, it imposes a variable receiver packet latency equivalent to the packet size.
IEEE 802.3 1G 1000 BaseX point to point Ethernet does not include any options for FEC. Data in IEEE 802.3 1G 1000 BaseX point to point Ethernet is typically transmitted as 10 bit symbols encoding 8 bit symbols so as to ensure balance on the transmission medium, in a process known as 8B/10B encoding.